1. Field of the Invention
The present invention relates to MOSFET devices and particularly to MOSFET devices used as low on-impedance switches.
2. Background Information
MOSFET switches are found in many applications and have become common in high frequency switch applications. As technology progressed, such transistor switches became smaller, faster and more power efficient. Often these low on-impedance switches are used to transfer logic data between systems using different power sources, say a 5V system sending and/or receiving logic signals from a 3V system. Typically the power sources determine the high logic levels. Such switches may couple logic systems powered from 5V, 3.3V and/or 1.8V to each other.
Operation at the lower power supply levels, however, encounters issues with respect to threshold requirements inherent in MOSFET transistors. For example, in systems with differing power sources, trouble might be encountered where a logic signal sent from a system is higher than the power supply of the receiving system. Over/under voltage effects are known to cause catastrophic MOSFET failures.
One such approach to alleviating the above limitation is discussed in U.S. Pat. No. 6,163,199 ('199), entitled: “Overvoltage/Undervoltage Tolerant Transfer Gate.” The '199 provides parallel transistors arranged for over under and under voltage protection. The '199 drives the back gates (bulk contacts) of the transfer transistors involved. The '199 patent is owned in common with the present application and shares a common inventor. The '199 patent provides a more detailed discussion of the limitations of the prior art along with an approach to help relieve the problem. The '199 patent is hereby incorporated herein by reference.
Other known designs have focused on lowering insertion loss and increasing the bandwidth by minimizing the “body effect” that is inherent in MOSFET structures. Insertion loss can be described, generally, as the loss of signal power delivered to a load due to the addition of a less than perfect switch compared to that if the switch were perfect.
The body effect becomes significant when the FET switch is turned on and neither the source nor the drain are at the same potential as the well. In such instances, the well acts like another gate (sometimes referred to as a “back gate”) and produces a localized increase in the threshold voltage which in turn reduces the conduction between source and drain. That is, the switch on-resistance increases which, in turn, reduces the device bandwidth due to a frequency roll-off with the capacitance present. Bandwidth is defined herein as the −3 dB point on the continuous curve of insertion loss versus frequency.
A representative prior art design focused on reducing the body effect and insertion loss is found in U.S. Pat. No. 5,818,099 ('099) to Burghartz. The '099 patent describes an n-type MOSFET structure with a p-well that is isolated from the p-type substrate using n-type well as shown in FIG. 6A of the '099 patent. This type of structure is now commonly used by many makers of such switches, and this same basic structure may be used for n-type MOSFET structures in preferred embodiments of the present invention. The '099 patent is hereby incorporated herein by reference.
The '099 low insertion loss circuit embodiment, however, may have larger leakage when there is a signal voltage present and the supply voltage to the transfer switch is turned off, e.g., when power is turned off first to the transfer switch before it is turned off at the sending or receiving systems. Moreover, the switch may become turned on when it should be off during power down.
For example, in the prior art of FIG. 1, a p-type MOSFET is shown with typical biasing of the well to +V. This ensures that the drain/source to well pn junction diode does not become forward biased. However, if the +V supply is at ground (by the supply being turned off) while there is a high logic level, say +5V, at terminal A, the pn drainwell diode in the MOSFET switch is forward biased creating a potentially harmful current path that charges the output capacitor of the +V supply. So the well of the p-type MOSFET will be charged and, thus, the switch is powered when it should be unpowered. Also, the capacitance from the drain and the source to the well, Cdw and Csw, respectively, act to limit the bandwidth of the switch.
There remains in prior art MOSFET switches limitations for over voltage protection during power down operations and for insertion and bandwidth loss. The present invention is directed, inter alia, towards these limitations.